From the title of this article, you probably assumed that it covers third-generation SerDes I/O interfaces such as PCI Express 3.0 or USB 3.0. While the principles described here certainly apply to ...
Goepel electronic’s AAPG (Automatic Application Program Generator) enables the design validation and testing of FPGA high-speed I/O based on ChipVORX FPGA-embedded ...
Needing to test the display interface for a multitude of different sensors [Fileark] built himself this analog and digital input/output simulator. Along the bottom is a double row of trimpots that ...
For both PCIe and Ethernet (IEEE 802.3,) signals are getting mighty small. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are ...
A new concept can execute the same boundary scan test pattern on various ATE systems without modification. Boundary scan is well established and widely used for various board- and system-level test ...
SAN JOSE, Calif. — July 8, 2005 — LogicVision, Inc. (NASDAQ: LGVN), a leading provider of yield learning capabilities that enable its customers to quickly and efficiently improve product yields, ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results