IEEE

A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter

Abstract: This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with ...
IEEE

A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pA rms , 400 V/s FSCV Sensing

Abstract: This paper describes a system-on-chip (SoC) fabricated in AMS 0.35 μm 2P/4M CMOS for high-fidelity neurochemical pattern generation in vivo. The SoC uniquely integrates electrical ...